/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/
/**
 * @file  ipc_hw_impl.h
 * @brief this file is used as ipc hardware layer implementation api definition, you should implement your own ipc driver in follow options.
 * @note
 * @details feature list
 */
#ifndef _IPC_HW_IMPL_H
#define _IPC_HW_IMPL_H

#include "ipc_hw_common.h"

#include "sys_base_reg.h"

/**
 * @brief reg addr offset
 * 
 */
#define MSGBX_END_CONFIG_OFFSET            (0x000U)
#define MSGBX_END_FLT1_CSR_OFFSET          (0x200U)
#define MSGBX_END_FLT2_CSR_OFFSET          (0x400U)
#define MSGBX_END_FLT3_CSR_OFFSET          (0x600U)
#define MSGBX_END_FMU_CSR_OFFSET           (0x8000U)
#define MSGBX_END_DE_RXFIFO_OFFSET         (0x10000U)
#define MSGBX_END_FLT1_RXFIFO_OFFSET       (0x10200U)
#define MSGBX_END_FLT2_RXFIFO_OFFSET       (0x10400U)
#define MSGBX_END_FLT3_RXFIFO_OFFSET       (0x10600U)
#define MSGBX_END_TXFIFO_OFFSET            (0x11000U)

/**
 * @brief default flt reg offset
 * 
 */
#define MSGBX_END_ABLT_R_OFFSET              (0x000U)
#define MSGBX_END_ABLT2_R_OFFSET             (0x008U)
#define END_DEFAULT_RXFIFO_ADDRR_OFFSET      (0x010U)
#define END_DEFAULT_MSGH_PIDF_CFGR_OFFSET    (0x018U)
#define END_TX_FIFO_THRES_OFFSET             (0x020U)
#define END_TX_FIFO_AVAILABLE_OFFSET         (0x028U)
#define END_DEFAULT_RXTHRS_CFGR_OFFSET       (0x030U)
#define END_DEFAULT_RXFIFO_STATUSR_OFFSET    (0x038U)
#define END_POOL_STATUS_REQR_OFFSET          (0x040U)
#define END_POOL_STATUS_R_OFFSET             (0x048U)
#define THIS_END_STATUS_R_OFFSET             (0x050U)
#define END_STATUSR_OFFSET                   (0x058U)
#define END_ENR_OFFSET                       (0x060U)
#define END_INTRR_OFFSET                     (0x068U)
#define TIMER_CFGR_OFFSET                    (0x070U)
#define VERSIONR_OFFSET                      (0x078U)

/**
 * @brief end flt reg addr offset
 * 
 */
#define END_FILTER1_RXFIFO_ADDRR_OFFSET        (0x00U)
#define END_FILTER1_MSGH_PIDF_CFGR_OFFSET      (0x08U)
#define END_FILTER1_MSGH_LENF_CFGR_OFFSET      (0x10U)
#define END_FILTER1_MSGH_RESF_MASKR_OFFSET     (0x18U)
#define END_FILTER1_MSGH_RESF_MASKHR_OFFSET    (0x20U)
#define END_FILTER1_MSGH_RESF_MINR_OFFSET      (0x28U)
#define END_FILTER1_MSGH_RESF_MINHR_OFFSET     (0x30U)
#define END_FILTER1_MSGH_RESF_MAXR_OFFSET      (0x38U)
#define END_FILTER1_MSGH_RESF_MAXHR_OFFSET     (0x40U)
#define END_FILTER1_MSGP1_MASKR_OFFSET         (0x48U)
#define END_FILTER1_MSGP1_MASKHR_OFFSET        (0x50U)
#define END_FILTER1_MSGP1_MINR_OFFSET          (0x58U)
#define END_FILTER1_MSGP1_MINHR_OFFSET         (0x60U)
#define END_FILTER1_MSGP1_MAXR_OFFSET          (0x68U)
#define END_FILTER1_MSGP1_MAXHR_OFFSET         (0x70U)
#define END_FILTER1_MSGP2_MASKR_OFFSET         (0x78U)
#define END_FILTER1_MSGP2_MASKHR_OFFSET        (0x80U)
#define END_FILTER1_MSGP2_MINR_OFFSET          (0x88U)
#define END_FILTER1_MSGP2_MINHR_OFFSET         (0x90U)
#define END_FILTER1_MSGP2_MAXR_OFFSET          (0x98U)
#define END_FILTER1_MSGP2_MAXHR_OFFSET         (0xA0U)
#define END_FILTER1_MSGP3_MASKR_OFFSET         (0xA8U)
#define END_FILTER1_MSGP3_MASKHR_OFFSET        (0xB0U)
#define END_FILTER1_MSGP3_MINR_OFFSET          (0xB8U)
#define END_FILTER1_MSGP3_MINHR_OFFSET         (0xC0U)
#define END_FILTER1_MSGP3_MAXR_OFFSET          (0xD0U)
#define END_FILTER1_MSGP3_MAXHR_OFFSET         (0xD8U)
#define END_FILTER1_MSGP4_MASKR_OFFSET         (0xE0U)
#define END_FILTER1_MSGP4_MASKHR_OFFSET        (0xE8U)
#define END_FILTER1_MSGP4_MINR_OFFSET          (0xF0U)
#define END_FILTER1_MSGP4_MINHR_OFFSET         (0xF8U)
#define END_FILTER1_MSGP4_MAXR_OFFSET          (0x100U)
#define END_FILTER1_MSGP4_MAXHR_OFFSET         (0x108U)
#define END_FILTER1_RXFIFO_CFGR_OFFSET         (0x110U)
#define END_FILTER_THRS_CFGR_OFFSET            (0x118U)
#define END_FILTER_RXFIFO_STATUSR_OFFSET       (0x120U)
#define END_FILTER_STATUSR_OFFSET              (0x128U)
#define END_FILTER_ENR_OFFSET                  (0x130U)
#define END_FILTER_INTRR_OFFSET                (0x138U)

/**
 * @brief end fmu reg addr offset
 * 
 */
#define MSGBX_FMU_SAFETY_INTR_ST_OFFSET     (0x000U)
#define MSGBX_FMU_SAFETY_INTR_EN_OFFSET     (0x008U)
#define MSGBX_FMU_SAFETY_INTR_CLR_OFFSET    (0x010U)
#define MSGBX_FMU_SAFETY_INTR_INJ_OFFSET    (0x018U)


#define MSGBX_END_ABLT_R_FILTER_NUM_U32                                         (0x00000E00UL) /*The Number of Filter installed in this Msgbx End*/
#define MSGBX_END_ABLT_R_FILTER_NUM_SHIFT_U32                                   (9U)
#define MSGBX_END_ABLT_R_IS_64_BIT_U32                                          (0x00000100UL) /*Indicate the Data width of this Msgbx End either 64 bit or 32 bit */
#define MSGBX_END_ABLT_R_IS_64_BIT_SHIFT_U32                                    (8U)
#define MSGBX_END_ABLT_R_MY_ID_U32                                              (0x000000FFUL) /*The ID of this MsgBx End*/
#define MSGBX_END_ABLT_R_MY_ID_SHIFT_U32                                        (0U)

#define MSGBX_END_ABLT2_R_TX_FIFO_DEPTH_U32                                     (0x000FFC00UL) /*8*/
#define MSGBX_END_ABLT2_R_TX_FIFO_DEPTH_SHIFT_U32                               (10U)
#define MSGBX_END_ABLT2_R_RX_FIFO_DEPTH_U32                                     (0x000003FFUL) /*16*/
#define MSGBX_END_ABLT2_R_RX_FIFO_DEPTH_SHIFT_U32                               (0U)

#define END_DEFAULT_RXFIFO_ADDRR_RX_FIFO_END_ADDR_U32                           (0x000FFC00UL) /*None*/
#define END_DEFAULT_RXFIFO_ADDRR_RX_FIFO_END_ADDR_SHIFT_U32                     (10U)
#define END_DEFAULT_RXFIFO_ADDRR_RX_FIFO_ST_ADDR_U32                            (0x000003FFUL) /*ֻ�Ƿ������ݴ�ŵĵ�ַ�������ݶ�ȡû��ϵ*/
#define END_DEFAULT_RXFIFO_ADDRR_RX_FIFO_ST_ADDR_SHIFT_U32                      (0U)

#define END_DEFAULT_MSGH_PIDF_CFGR_RX_FILTER_EN_U32                             (0x80000000UL) /*Enable the filter to filte message based on the PID*/
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_FILTER_EN_SHIFT_U32                       (31U)
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_FILTER_INVERT_U32                     (0x40000000UL) /*0: Receive the message that falls into the ranve set by Rx_PID_st nad Rx_PID_end, 1:Discared*/
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_FILTER_INVERT_SHIFT_U32               (30U)
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_END_U32                               (0x0000FF00UL) /*None*/
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_END_SHIFT_U32                         (8U)
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_ST_U32                                (0x000000FFUL) /*None*/
#define END_DEFAULT_MSGH_PIDF_CFGR_RX_PID_ST_SHIFT_U32                          (0U)

#define END_TX_FIFO_THRES_END_TX_FIFO_THRES_U32                                 (0x000003FFUL) /*None*/
#define END_TX_FIFO_THRES_END_TX_FIFO_THRES_SHIFT_U32                           (0U)

#define END_TX_FIFO_AVAILABLE_END_TX_FIFO_AVAILABLE_U32                         (0x000003FFUL) /*None*/
#define END_TX_FIFO_AVAILABLE_END_TX_FIFO_AVAILABLE_SHIFT_U32                   (0U)

#define END_DEFAULT_RXTHRS_CFGR_DEFAULT_RXFIFO_THRESHOLD_U32                    (0x000003FFUL) /*The register that set the threshold to generate the default_rx_overflow interrupt*/
#define END_DEFAULT_RXTHRS_CFGR_DEFAULT_RXFIFO_THRESHOLD_SHIFT_U32              (0U)

#define END_DEFAULT_RXFIFO_STATUSR_DEFAULT_RXFIFO_STATUS_U32                    (0x000003FFUL) /*The Number of messages that have not been handled*/
#define END_DEFAULT_RXFIFO_STATUSR_DEFAULT_RXFIFO_STATUS_SHIFT_U32              (0U)

#define END_POOL_STATUS_REQR_TARGET_END_ID_U32                                  (0x000000FFUL) /*None*/
#define END_POOL_STATUS_REQR_TARGET_END_ID_SHIFT_U32                            (0U)

#define END_POOL_STATUS_R_TARGET_END_STATUS_U32                                 (0xFFFFFFFFUL) /*The status of the target Msgbx End*/
#define END_POOL_STATUS_R_TARGET_END_STATUS_SHIFT_U32                           (0U)

#define THIS_END_STATUS_R_THIS_END_STATUS_U32                                   (0xFFFFFFFFUL) /*The status of this Msgbx End*/
#define THIS_END_STATUS_R_THIS_END_STATUS_SHIFT_U32                             (0U)

#define END_STATUSR_MSGBX_END_POOL_STATUS_U32                                   (0x00000020UL) /*None*/
#define END_STATUSR_MSGBX_END_POOL_STATUS_SHIFT_U32                             (5U)
#define END_STATUSR_TX_OVERFLOW_U32                                             (0x00000010UL) /*None*/
#define END_STATUSR_TX_OVERFLOW_SHIFT_U32                                       (4U)
#define END_STATUSR_TX_THRS_U32                                                 (0x00000008UL) /*None*/
#define END_STATUSR_TX_THRS_SHIFT_U32                                           (3U)
#define END_STATUSR_DEFAULT_RX_OVERFLOW_U32                                     (0x00000004UL) /*None*/
#define END_STATUSR_DEFAULT_RX_OVERFLOW_SHIFT_U32                               (2U)
#define END_STATUSR_DEFAULT_RX_UNDERFLOW_U32                                    (0x00000002UL) /*None*/
#define END_STATUSR_DEFAULT_RX_UNDERFLOW_SHIFT_U32                              (1U)
#define END_STATUSR_DEFAULT_RX_THRS_U32                                         (0x00000001UL) /*None*/
#define END_STATUSR_DEFAULT_RX_THRS_SHIFT_U32                                   (0U)

#define END_ENR_MSGBX_END_POOL_STATUS_INTR_EN_U32                               (0x00000020UL) /*None*/
#define END_ENR_MSGBX_END_POOL_STATUS_INTR_EN_SHIFT_U32                         (5U)
#define END_ENR_TX_OVERFLOW_INTR_EN_U32                                         (0x00000010UL) /*None*/
#define END_ENR_TX_OVERFLOW_INTR_EN_SHIFT_U32                                   (4U)
#define END_ENR_TX_THRS_INTR_EN_U32                                             (0x00000008UL) /*None*/
#define END_ENR_TX_THRS_INTR_EN_SHIFT_U32                                       (3U)
#define END_ENR_DEFAULT_RX_OVERFLOW_INTR_EN_U32                                 (0x00000004UL) /*None*/
#define END_ENR_DEFAULT_RX_OVERFLOW_INTR_EN_SHIFT_U32                           (2U)
#define END_ENR_DEFAULT_RX_UNDERFLOW_INTR_EN_U32                                (0x00000002UL) /*None*/
#define END_ENR_DEFAULT_RX_UNDERFLOW_INTR_EN_SHIFT_U32                          (1U)
#define END_ENR_DEFAULT_RX_THRS_INTR_EN_U32                                     (0x00000001UL) /*None*/
#define END_ENR_DEFAULT_RX_THRS_INTR_EN_SHIFT_U32                               (0U)

#define END_INTRR_MSGBX_END_POOL_STATUS_INTR_U32                                (0x00000020UL) /*None*/
#define END_INTRR_MSGBX_END_POOL_STATUS_INTR_SHIFT_U32                          (5U)
#define END_INTRR_TX_OVERFLOW_INTR_U32                                          (0x00000010UL) /*None*/
#define END_INTRR_TX_OVERFLOW_INTR_SHIFT_U32                                    (4U)
#define END_INTRR_TX_THRS_INTR_U32                                              (0x00000008UL) /*None*/
#define END_INTRR_TX_THRS_INTR_SHIFT_U32                                        (3U)
#define END_INTRR_DEFAULT_RX_OVERFLOW_INTR_U32                                  (0x00000004UL) /*None*/
#define END_INTRR_DEFAULT_RX_OVERFLOW_INTR_SHIFT_U32                            (2U)
#define END_INTRR_DEFAULT_RX_UNDERFLOW_INTR_U32                                 (0x00000002UL) /*None*/
#define END_INTRR_DEFAULT_RX_UNDERFLOW_INTR_SHIFT_U32                           (1U)
#define END_INTRR_DEFAULT_RX_THRS_INTR_U32                                      (0x00000001UL) /*None*/
#define END_INTRR_DEFAULT_RX_THRS_INTR_SHIFT_U32                                (0U)

#define TIMER_CFGR_TIMER_EN_U32                                                 (0x80000000UL) /*None*/
#define TIMER_CFGR_TIMER_EN_SHIFT_U32                                           (31U)
#define TIMER_CFGR_TIMER_VALUE_U32                                              (0x3FFFFFFFUL) /*None*/
#define TIMER_CFGR_TIMER_VALUE_SHIFT_U32                                        (0U)

#define VERSIONR_VERSION_U32                                                    (0x0000000FUL) /*None*/
#define VERSIONR_VERSION_SHIFT_U32                                              (0U)

#define END_FILTER1_RXFIFO_ADDRR_RX_FILTER_EN_U32                                    (0x80000000UL) /*None*/
#define END_FILTER1_RXFIFO_ADDRR_RX_FILTER_EN_SHIFT_U32                              (31U)
#define END_FILTER1_RXFIFO_ADDRR_RX_FIFO_END_ADDR_U32                                (0x000FFC00UL) /*None*/
#define END_FILTER1_RXFIFO_ADDRR_RX_FIFO_END_ADDR_SHIFT_U32                          (10U)
#define END_FILTER1_RXFIFO_ADDRR_RX_FIFO_ST_ADDR_U32                                 (0x000003FFUL) /*None*/
#define END_FILTER1_RXFIFO_ADDRR_RX_FIFO_ST_ADDR_SHIFT_U32                           (0U)

#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_FILTER_EN_U32                              (0x80000000UL) /*None*/
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_FILTER_EN_SHIFT_U32                        (31U)
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_FILTER_INVERT_U32                          (0x40000000UL) /*0: Receive the message that falls into the ranve set by Rx_PID_st nad Rx_PID_end, 1:Discared*/
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_FILTER_INVERT_SHIFT_U32                    (30U)
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_END_U32                                    (0x0000FF00UL) /*None*/
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_END_SHIFT_U32                              (8U)
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_ST_U32                                     (0x000000FFUL) /*None*/
#define END_FILTER1_MSGH_PIDF_CFGR_RX_PID_ST_SHIFT_U32                               (0U)

#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_FILTER_EN_U32                              (0x80000000UL) /*None*/
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_FILTER_EN_SHIFT_U32                        (31U)
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_FILTER_INVERT_U32                          (0x40000000UL) /*None*/
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_FILTER_INVERT_SHIFT_U32                    (30U)
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_END_U32                                    (0x000000F0UL) /*None*/
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_END_SHIFT_U32                              (4U)
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_ST_U32                                     (0x0000000FUL) /*None*/
#define END_FILTER1_MSGH_LENF_CFGR_RX_LEN_ST_SHIFT_U32                               (0U)

#define END_FILTER1_MSGH_RESF_MASKR_RX_RESERVED_FILTER_MASK_U32                      (0xFFF00000UL) /*Select the bits of Reserved field of Message Header to be compared*/
#define END_FILTER1_MSGH_RESF_MASKR_RX_RESERVED_FILTER_MASK_SHIFT_U32                (20U)

#define END_FILTER1_MSGH_RESF_MASKHR_RX_RESERVEDH_FILTER_MASK_U32                    (0xFFFFFFFFUL) /*Select the bits of Reserved field of the higher 32 bits of Message Header to be compared, Only exits in the 64-bit Msgbx End*/
#define END_FILTER1_MSGH_RESF_MASKHR_RX_RESERVEDH_FILTER_MASK_SHIFT_U32              (0U)

#define END_FILTER1_MSGH_RESF_MINR_RX_RES_MIN_U32                                    (0xFFF00000UL) /*The minimal Reserved value that is cared.*/
#define END_FILTER1_MSGH_RESF_MINR_RX_RES_MIN_SHIFT_U32                              (20U)

#define END_FILTER1_MSGH_RESF_MINHR_RX_RESH_MINH_U32                                 (0xFFFFFFFFUL) /*The minimal Reserved value that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGH_RESF_MINHR_RX_RESH_MINH_SHIFT_U32                           (0U)

#define END_FILTER1_MSGH_RESF_MAXR_RX_RES_MAX_U32                                    (0xFFF00000UL) /*The maximal Reserved value that is cared.*/
#define END_FILTER1_MSGH_RESF_MAXR_RX_RES_MAX_SHIFT_U32                              (20U)

#define END_FILTER1_MSGH_RESF_MAXHR_RX_RESH_MAXH_U32                                 (0xFFFFFFFFUL) /*The maximal Reserved value that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGH_RESF_MAXHR_RX_RESH_MAXH_SHIFT_U32                           (0U)

#define END_FILTER1_MSGP1_MASKR_RX_MSGP1_FILTER_MASK_U32                             (0xFFFFFFFFUL) /*Select the bits of Message payload1 to be compared*/
#define END_FILTER1_MSGP1_MASKR_RX_MSGP1_FILTER_MASK_SHIFT_U32                       (0U)

#define END_FILTER1_MSGP1_MASKHR_RX_MSGPH1_FILTER_MASK_U32                           (0xFFFFFFFFUL) /*Select the bits of the higher 32 bits of Message payload1 to be compared, Only exits in the 64-bit Msgbx End*/
#define END_FILTER1_MSGP1_MASKHR_RX_MSGPH1_FILTER_MASK_SHIFT_U32                     (0U)

#define END_FILTER1_MSGP1_MINR_RX_MSGP1_MIN_U32                                      (0xFFFFFFFFUL) /*The minimal Message payload1 value that is cared.*/
#define END_FILTER1_MSGP1_MINR_RX_MSGP1_MIN_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP1_MINHR_RX_MSGPH1_MINH_U32                                   (0xFFFFFFFFUL) /*The minimal Message payload1 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP1_MINHR_RX_MSGPH1_MINH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP1_MAXR_RX_MSGP1_MAX_U32                                      (0xFFFFFFFFUL) /*The maximal Message payload1 that is cared.*/
#define END_FILTER1_MSGP1_MAXR_RX_MSGP1_MAX_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP1_MAXHR_RX_MSGPH1_MAXH_U32                                   (0xFFFFFFFFUL) /*The maximal Message payload1 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP1_MAXHR_RX_MSGPH1_MAXH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP2_MASKR_RX_MSGP2_FILTER_MASK_U32                             (0xFFFFFFFFUL) /*Select the bits of Message Payload2 to be compared*/
#define END_FILTER1_MSGP2_MASKR_RX_MSGP2_FILTER_MASK_SHIFT_U32                       (0U)

#define END_FILTER1_MSGP2_MASKHR_RX_MSGPH2_FILTER_MASK_U32                           (0xFFFFFFFFUL) /*Select the bits of the higher 32 bits of Message Payload2 to be compared, Only exits in the 64-bit Msgbx End*/
#define END_FILTER1_MSGP2_MASKHR_RX_MSGPH2_FILTER_MASK_SHIFT_U32                     (0U)

#define END_FILTER1_MSGP2_MINR_RX_MSGP2_MIN_U32                                      (0xFFFFFFFFUL) /*The minimal Message Payload2 value that is cared.*/
#define END_FILTER1_MSGP2_MINR_RX_MSGP2_MIN_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP2_MINHR_RX_MSGPH2_MINH_U32                                   (0xFFFFFFFFUL) /*The minimal Message Payload2 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP2_MINHR_RX_MSGPH2_MINH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP2_MAXR_RX_MSGP2_MAX_U32                                      (0xFFFFFFFFUL) /*The maximal Message Payload2 that is cared.*/
#define END_FILTER1_MSGP2_MAXR_RX_MSGP2_MAX_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP2_MAXHR_RX_MSGPH2_MAXH_U32                                   (0xFFFFFFFFUL) /*The maximal Message Payload2 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP2_MAXHR_RX_MSGPH2_MAXH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP3_MASKR_RX_MSGP3_FILTER_MASK_U32                             (0xFFFFFFFFUL) /*Select the bits of Message Payload3 to be compared*/
#define END_FILTER1_MSGP3_MASKR_RX_MSGP3_FILTER_MASK_SHIFT_U32                       (0U)

#define END_FILTER1_MSGP3_MASKHR_RX_MSGPH3_FILTER_MASK_U32                           (0xFFFFFFFFUL) /*Select the bits of the higher 32 bits of Message Payload3 to be compared, Only exits in the 64-bit Msgbx End*/
#define END_FILTER1_MSGP3_MASKHR_RX_MSGPH3_FILTER_MASK_SHIFT_U32                     (0U)

#define END_FILTER1_MSGP3_MINR_RX_MSGP3_MIN_U32                                      (0xFFFFFFFFUL) /*The minimal Message Payload3 value that is cared.*/
#define END_FILTER1_MSGP3_MINR_RX_MSGP3_MIN_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP3_MINHR_RX_MSGPH3_MINH_U32                                   (0xFFFFFFFFUL) /*The minimal Message Payload3 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP3_MINHR_RX_MSGPH3_MINH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP3_MAXR_RX_MSGP3_MAX_U32                                      (0xFFFFFFFFUL) /*The maximal Message Payload3 that is cared.*/
#define END_FILTER1_MSGP3_MAXR_RX_MSGP3_MAX_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP3_MAXHR_RX_MSGPH3_MAXH_U32                                   (0xFFFFFFFFUL) /*The maximal Message Payload3 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP3_MAXHR_RX_MSGPH3_MAXH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP4_MASKR_RX_MSGP4_FILTER_MASK_U32                             (0xFFFFFFFFUL) /*Select the bits of Message Payload4 to be compared*/
#define END_FILTER1_MSGP4_MASKR_RX_MSGP4_FILTER_MASK_SHIFT_U32                       (0U)

#define END_FILTER1_MSGP4_MASKHR_RX_MSGPH4_FILTER_MASK_U32                           (0xFFFFFFFFUL) /*Select the bits of the higher 32 bits of Message Payload4 to be compared, Only exits in the 64-bit Msgbx End*/
#define END_FILTER1_MSGP4_MASKHR_RX_MSGPH4_FILTER_MASK_SHIFT_U32                     (0U)

#define END_FILTER1_MSGP4_MINR_RX_MSGP4_MIN_U32                                      (0xFFFFFFFFUL) /*The minimal Message Payload4 value that is cared.*/
#define END_FILTER1_MSGP4_MINR_RX_MSGP4_MIN_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP4_MINHR_RX_MSGPH4_MINH_U32                                   (0xFFFFFFFFUL) /*The minimal Message Payload4 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP4_MINHR_RX_MSGPH4_MINH_SHIFT_U32                             (0U)

#define END_FILTER1_MSGP4_MAXR_RX_MSGP4_MAX_U32                                      (0xFFFFFFFFUL) /*The maximal Message Payload4 that is cared.*/
#define END_FILTER1_MSGP4_MAXR_RX_MSGP4_MAX_SHIFT_U32                                (0U)

#define END_FILTER1_MSGP4_MAXHR_RX_MSGPH4_MAXH_U32                                   (0xFFFFFFFFUL) /*The maximal Message Payload4 that is cared, for higher bit of Reserved field, only exits in the 64-bit Msgbx End.*/
#define END_FILTER1_MSGP4_MAXHR_RX_MSGPH4_MAXH_SHIFT_U32                             (0U)

#define END_FILTER1_RXFIFO_CFGR_FILTER_COMBI_MODE_U32                                (0xC0000000UL) /*2'b00: logic AND of all the result of the comparators, 2'b01: logic OR, Others: Reserved.*/
#define END_FILTER1_RXFIFO_CFGR_FILTER_COMBI_MODE_SHIFT_U32                          (30U)
#define END_FILTER1_RXFIFO_CFGR_MSGP4_COMBI_LH_COMP_U32                              (0x00020000UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP4_COMBI_LH_COMP_SHIFT_U32                        (17U)
#define END_FILTER1_RXFIFO_CFGR_MSGP3_COMBI_LH_COMP_U32                              (0x00010000UL) /*��32λ�͵�32λ����һ��Ƚϣ�64λϵͳ��*/
#define END_FILTER1_RXFIFO_CFGR_MSGP3_COMBI_LH_COMP_SHIFT_U32                        (16U)
#define END_FILTER1_RXFIFO_CFGR_MSGP2_COMBI_LH_COMP_U32                              (0x00008000UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP2_COMBI_LH_COMP_SHIFT_U32                        (15U)
#define END_FILTER1_RXFIFO_CFGR_MSGP1_COMBI_LH_COMP_U32                              (0x00004000UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP1_COMBI_LH_COMP_SHIFT_U32                        (14U)
#define END_FILTER1_RXFIFO_CFGR_MSGH_COMBI_LH_COMP_U32                               (0x00002000UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGH_COMBI_LH_COMP_SHIFT_U32                         (13U)
#define END_FILTER1_RXFIFO_CFGR_MSGP4_FILTER_INVERT_U32                              (0x00001000UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP4_FILTER_INVERT_SHIFT_U32                        (12U)
#define END_FILTER1_RXFIFO_CFGR_MSGP3_FILTER_INVERT_U32                              (0x00000800UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP3_FILTER_INVERT_SHIFT_U32                        (11U)
#define END_FILTER1_RXFIFO_CFGR_MSGP2_FILTER_INVERT_U32                              (0x00000400UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP2_FILTER_INVERT_SHIFT_U32                        (10U)
#define END_FILTER1_RXFIFO_CFGR_MSGP1_FILTER_INVERT_U32                              (0x00000200UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP1_FILTER_INVERT_SHIFT_U32                        (9U)
#define END_FILTER1_RXFIFO_CFGR_MSGH_FLILTER_INVERT_U32                              (0x00000100UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGH_FLILTER_INVERT_SHIFT_U32                        (8U)
#define END_FILTER1_RXFIFO_CFGR_MSGP4_FILTER_EN_U32                                  (0x00000010UL) /*ʹ��ǰ��Ҫ���ú�min��max��bit_mask������������msg��filter����û�ж�Ӧ��msgҲ��ƥ�����*/
#define END_FILTER1_RXFIFO_CFGR_MSGP4_FILTER_EN_SHIFT_U32                            (4U)
#define END_FILTER1_RXFIFO_CFGR_MSGP3_FILTER_EN_U32                                  (0x00000008UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP3_FILTER_EN_SHIFT_U32                            (3U)
#define END_FILTER1_RXFIFO_CFGR_MSGP2_FILTER_EN_U32                                  (0x00000004UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP2_FILTER_EN_SHIFT_U32                            (2U)
#define END_FILTER1_RXFIFO_CFGR_MSGP1_FILTER_EN_U32                                  (0x00000002UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGP1_FILTER_EN_SHIFT_U32                            (1U)
#define END_FILTER1_RXFIFO_CFGR_MSGH_FLILTER_EN_U32                                  (0x00000001UL) /*None*/
#define END_FILTER1_RXFIFO_CFGR_MSGH_FLILTER_EN_SHIFT_U32                            (0U)

#define END_FILTER_THRS_CFGR_FILTER_THRESHOLD_U32                                    (0x000003FFUL) /*None*/
#define END_FILTER_THRS_CFGR_FILTER_THRESHOLD_SHIFT_U32                              (0U)

#define END_FILTER_RXFIFO_STATUSR_FILTER_RXFIFO_STATUS_U32                           (0x000003FFUL) /*None*/
#define END_FILTER_RXFIFO_STATUSR_FILTER_RXFIFO_STATUS_SHIFT_U32                     (0U)

#define END_FILTER_STATUSR_FILTER_OVERFLOW_U32                                       (0x00000004UL) /*None*/
#define END_FILTER_STATUSR_FILTER_OVERFLOW_SHIFT_U32                                 (2U)
#define END_FILTER_STATUSR_FILTER_UNDERFLOW_U32                                      (0x00000002UL) /*None*/
#define END_FILTER_STATUSR_FILTER_UNDERFLOW_SHIFT_U32                                (1U)
#define END_FILTER_STATUSR_FILTER_THRS_U32                                           (0x00000001UL) /*None*/
#define END_FILTER_STATUSR_FILTER_THRS_SHIFT_U32                                     (0U)

#define END_FILTER_ENR_FILTER_OVERFLOW_INTR_EN_U32                                   (0x00000004UL) /*None*/
#define END_FILTER_ENR_FILTER_OVERFLOW_INTR_EN_SHIFT_U32                             (2U)
#define END_FILTER_ENR_FILTER_UNDERFLOW_INTR_EN_U32                                  (0x00000002UL) /*None*/
#define END_FILTER_ENR_FILTER_UNDERFLOW_INTR_EN_SHIFT_U32                            (1U)
#define END_FILTER_ENR_FILTER_THRS_INTR_EN_U32                                       (0x00000001UL) /*None*/
#define END_FILTER_ENR_FILTER_THRS_INTR_EN_SHIFT_U32                                 (0U)

#define END_FILTER_INTRR_FILTER_OVERFLOW_INTR_U32                                    (0x00000004UL) /*None*/
#define END_FILTER_INTRR_FILTER_OVERFLOW_INTR_SHIFT_U32                              (2U)
#define END_FILTER_INTRR_FILTER_UNDERFLOW_INTR_U32                                   (0x00000002UL) /*None*/
#define END_FILTER_INTRR_FILTER_UNDERFLOW_INTR_SHIFT_U32                             (1U)
#define END_FILTER_INTRR_FILTER_THRS_INTR_U32                                        (0x00000001UL) /*None*/
#define END_FILTER_INTRR_FILTER_THRS_INTR_SHIFT_U32                                  (0U)

#define PID_MSG_END \
        MSG_END_MACRO(PID_CMN_MSG_END0,        0x10) \
        MSG_END_MACRO(PID_CMN_MSG_END1,        0x11) \
        MSG_END_MACRO(PID_CMN_MSG_END2,        0x12) \
        MSG_END_MACRO(PID_CMN_MSG_END3,        0x13) \
        MSG_END_MACRO(PID_CMN_MSG_END4,        0x14) \
        MSG_END_MACRO(PID_CMN_MSG_END5,        0x15) \
        MSG_END_MACRO(PID_CMN_MSG_END6,        0x16) \
        MSG_END_MACRO(PID_CMN_MSG_END7,        0x17) \
        MSG_END_MACRO(PID_DB_MSG_END0,         0x20) \
        MSG_END_MACRO(PID_DB_MSG_END1,         0x21) \
        MSG_END_MACRO(PID_ISPCV_MSG_END0,      0x30) \
        MSG_END_MACRO(PID_ISPCV_MSG_END1,      0x31) \
        MSG_END_MACRO(PID_ISPCV_MSG_END2,      0x32) \
        MSG_END_MACRO(PID_ISPCV_MSG_END3,      0x33) \
        MSG_END_MACRO(PID_ISPCV_MSG_END4,      0x34) \
        MSG_END_MACRO(PID_NET_MSG_END0,        0x40) \
        MSG_END_MACRO(PID_DMA_MSG_END0,        0x50) \
        MSG_END_MACRO(PID_DMA_MSG_END1,        0x51) \
        MSG_END_MACRO(PID_R5_SW_MSG_END0,      0x60) \
        MSG_END_MACRO(PID_R5_SW_MSG_END1,      0x61) \
        MSG_END_MACRO(PID_R5_SW_MSG_END2,      0x62) \
        MSG_END_MACRO(PID_R5_SW_MSG_END3,      0x63) \
        MSG_END_MACRO(PID_R5_SW_MSG_END4,      0x64) \
        MSG_END_MACRO(PID_R5_SW_MSG_END5,      0x65) \
        MSG_END_MACRO(PID_R5_SECURE_EDN0,      0x70) \
        MSG_END_MACRO(PID_R5_SECURE_EDN1,      0x71) \
        MSG_END_MACRO(PID_R5_SAFETY_END0,      0x80) \
        MSG_END_MACRO(PID_R5_SAFETY_END1,      0x81) \
        MSG_END_MACRO(PID_R5_REALTIME_END0,    0x90) \
        MSG_END_MACRO(PID_R5_REALTIME_END1,    0x91) \
        MSG_END_MACRO(PID_R5_REALTIME_END2,    0x92) \
        MSG_END_MACRO(PID_R5_REALTIME_END3,    0x93) \
        MSG_END_MACRO(PID_R5_REALTIME_END4,    0x94) \
        MSG_END_MACRO(PID_R5_REALTIME_END5,    0x95) \
        MSG_END_MACRO(PID_MEDIA_MSG_END0,      0xA0)

typedef enum{
    #define MSG_END_MACRO(id, num) id = num,
        PID_MSG_END
    #undef MSG_END_MACRO
}msgbox_pid_types;

// this is the header file for hardware implementation, the core developer should follow these definition
// to implement related hardware function.

/********************* extern global function *******************/
// NOTE: please keep these extern function declarations in your own code, they are requiered api for you
// ipc_hw_layer recv msg notify, hw_impl_layer would call this function when interrupts receive message
extern int32_t ipc_hw_recv_msg_notify(const uint8_t endid, const uint8_t fid,
				      const rw_msg_t *msg);
// ipc_hw_layer error msg notify, hw_impl_layer would call this function when it receive error state
extern int32_t ipc_hw_err_msg_notify(const uint8_t endid, const uint8_t fid);

// api definition
struct _libipc_hw_compat_ops_t {
	//note: this label is used for multi-end, please refer to programmer guide for more details.
	uint8_t cpuid;
	int32_t (*ipc_hw_init)(const uint8_t endid,
			       const ipc_init_params_t *ipc_param);
	int32_t (*ipc_hw_deinit)(const uint8_t endid);

	// msgbx spec init
	int32_t (*ipc_hw_get_info)(const uint8_t endid,
				   msgbx_hw_info_t *hw_info);

	// msgbx filtering rule config
	int32_t (*ipc_hw_set_flt_cfg)(const uint8_t endid, const uint8_t flt_id,
				      const msgbx_flt_rule_cfg_t *rule);
	int32_t (*ipc_hw_clr_flt_cfg)(const uint8_t endid,
				      const uint8_t flt_id);
	int32_t (*ipc_hw_get_flt_info)(
		const uint8_t endid, const uint8_t flt_id,
		msgbx_flt_rule_cfg_t *info); //debug get rule setting

	// msgbx send msg * recv msg
	int32_t (*ipc_hw_send_msg)(const uint8_t endid, const rw_msg_t *msg);
	int32_t (*ipc_hw_get_msg)(const uint8_t endid, rw_msg_t *msg,
				  const uint8_t fid);

	// msgbx spec req
	int32_t (*ipc_hw_get_time)(uint64_t *timestamp);

	// msgbx state management
	// flag define see state management enable flag bit
	int32_t (*ipc_hw_sts_mgt_enble)(const uint8_t endid,
					const uint32_t flag);
	int32_t (*ipc_hw_sts_mgt_disable)(const uint8_t endid);

	// msgbx filter state management config
	int32_t (*ipc_hw_flt_mgt_enble)(const uint8_t endid,
					const uint8_t flt_id,
					const uint8_t flag);
	int32_t (*ipc_hw_flt_mgt_disable)(const uint8_t endid,
					  const uint8_t flt_id);

	// msgbx get error msg
	int32_t (*ipc_hw_get_err_msg)(const uint8_t endid, const uint8_t flt_id,
				      msgbx_err_msg_t *err_msg);

	// msgbx fault handle
	int32_t (*ipc_hw_err_hdl)(const uint8_t endid, uint8_t type, uint8_t id,
				  uint32_t hdl);
};
#define libipc_hw_compat_ops_t struct _libipc_hw_compat_ops_t

#endif
